1. Field of the Invention
The present invention relates to an improved dynamic semiconductive memory device, and more particularly to a dynamic semiconductive memory device capable of storing more than one bit in a cell.
2. Background Information
Although high integration techniques have permitted increasingly dense topographies in dynamic semiconductor memory fabrication, the constitution of the memory cell employing two elements consisting of one transistor and one capacitor per bit has not changed.
A typical dynamic semiconductor memory device is shown in FIG. 1. In FIG. 1, reference numeral 20 indicates a memory cell in a conventional dynamic semiconductor memory system. Memory cell 20 comprises a storage capacitor 21, a storage node 23 and a transfer gate transistor 22 for use in selecting the memory cell.
Reductions in the size of a memory cell such as cell 20 are limited by the capacitance required in capacitor 21 to avoid excessive soft errors due to alpha particles. Therefor further integration has been marked by attempts to reduce the area covered by a capacitor 21 while keeping its capacitance approximately the same. These attempts have led to three-dimensional structures such as grooves or stacks.
However, there are many problems in the production of such a three-dimensional memory cell and the development time needed to develop such a cell is burdensome.